Conventionally, it is known that information in a memory can be corrupted (for instance, a bit stating “1” may change to “0”), in other words, a soft error may occur, due to a cause such as an α beam or a neutron beam being irradiated onto the memory (see, for example, Japanese Patent Laid-open No. 8-137764).
A type of PLD is known which allows configuration of a logical circuit having a configuration indicated by circuit configuration information contained in a memory (information indicating the configuration of the logical circuit). One type of a PLD of this kind is an FPGA (Field Programmable Gate Array). An FPGA comprises, for example, a circuit element group comprising a plurality of circuit elements, and a memory for configuring a logical circuit on this circuit element group (hereinafter, called a “configuration memory”). A logical circuit having a configuration indicated by the circuit configuration information in the configuration memory is configured on the circuit element group. If a soft error occurs in the configuration memory, then the circuit configuration information in the case of the soft error will be different from the initial information, and there is a possibility that the logical circuit in the FPGA may be rewritten with a circuit having an unintended configuration.
Recently, there have been advances in the miniaturization and capacity of FPGAs, and accordingly, it has become possible to miniaturize the configuration memory, also. Therefore, the information in the configuration memory becomes more liable to the effects of radiation, and there is a possibility that the occurrence rate of soft errors may increase. Consequently, it has become impossible to ignore the occurrence of soft errors.
An FPGA may be fitted with an error monitoring function which checks whether or not a soft error has occurred in the configuration memory. When a soft error has occurred according to this error monitoring function, then the occurrence of a soft error is reported.
Soft errors that occur may or may not have an actual effect on the configured logical circuit. However, regardless of this, if a soft error has occurred according to the error monitoring function installed in the FPGA, then the occurrence of a soft error is reported. Therefore, it is not possible to implement control in accordance with whether or not an occurring soft error actually has an effect on the configured logical circuit. For example, one method for recovering from a soft error is a method in which the main power supply of the device in which the FPGA is installed is temporarily switched off and the main power supply of that device is then switched on again. However, if the main power supply is switched off each time a soft error occurs, then the usability of the device will be poor. This method is particularly undesirable in cases where the device in which the FPGA is installed is a device which does not permit a long-term halt in operation (namely, a “non-stop device”), and more specifically, for example, a storage system which is required to operate 24 hours a day.